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Integrated Circuit Systems, Inc.
ICS9FG104
Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
Recommended Application: Pin Configuration Frequency Timing Generator for Differential CPU & SATA clocks XIN/CLKIN 1 Features: * Generates common CPU frequencies from 14.318 MHz or 25 MHz * Crystal or reference input * 4 - 0.7V current-mode differential output pairs * Supports Serial-ATA at 100 MHz * Two spread spectrum modes: 0 to -0.5 downspread and +/-0.25% centerspread * Unused inputs may be disabled in either driven or Hi-Z state for power management. * M/N Programming Key Specifications: * Output cycle-to-cycle jitter < 50 ps * Output to output skew < 35 ps * +/-300 ppm frequency accuracy on output clocks
X2 VDD GND REFOUT FS2 DIF_3 DIF_3# VDD GND DIF_2 DIF_2# SDATA SCLK
2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDDA GNDA IREF FS0 FS1 DIF_0 DIF_0# VDD GND DIF_1 DIF_1# SEL14M_25M# SPREAD DIF_STOP#
28-pin SSOP/TSSOP
Frequency Select Table SEL14M_25M# FS2 FS1 FS0 OUTPUT(MHz) (FS3) 0 0 0 0 100.00 0 0 0 1 125.00 0 0 1 0 133.33 0 0 1 1 166.67 0 1 0 0 200.00 0 1 0 1 266.00 0 1 1 0 333.00 0 1 1 1 400.00 1 0 0 0 100.00 1 0 0 1 125.00 1 0 1 0 133.33 1 0 1 1 166.67 1 1 0 0 200.00 1 1 0 1 266.00 1 1 1 0 333.00 1 1 1 1 400.00
0839D--06/02/05
ICS9FG104
Integrated Circuit Systems, Inc.
ICS9FG104
Pin Description
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PIN NAME XIN/CLKIN X2 VDD GND REFOUT FS2 DIF_3 DIF_3# VDD GND DIF_2 DIF_2# SDATA SCLK DIF_STOP# SPREAD SEL14M_25M# DIF_1# DIF_1 GND VDD DIF_0# DIF_0 FS1 FS0 IREF GNDA VDDA PIN TYPE IN OUT PWR IN IN IN IN OUT PWR PWR OUT OUT I/O IN IN IN IN OUT OUT PWR PWR OUT OUT IN IN OUT PWR PWR DESCRIPTION Crystal input or Reference Clock input Crystal output, Nominally 14.318MHz Power supply, nominal 3.3V Ground pin. Reference Clock output Frequency select pin. 0.7V differential true clock outputs 0.7V differential complement clock outputs Power supply, nominal 3.3V Ground pin. 0.7V differential true clock outputs 0.7V differential complement clock outputs Data pin for SMBus circuitry, 5V tolerant. Clock pin of SMBus circuitry, 5V tolerant. Active low input to stop differential output clocks. Asynchronous, active high input, with internal 120Kohm pull-up resistor, to enable spread spectrum functionality. Select 14.31818 MHz or 25 Mhz input frequency. 1 = 14.31818 MHz, 0 = 25 MHz 0.7V differential complement clock outputs 0.7V differential true clock outputs Ground pin. Power supply, nominal 3.3V 0.7V differential complement clock outputs 0.7V differential true clock outputs Frequency select pin. Frequency select pin. This pin establishes the reference current for the differential currentmode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core.
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Integrated Circuit Systems, Inc.
ICS9FG104
General Description
The ICS9FG104 is a Frequency Timing Generator that provides 4 differential output pairs that are compliant to the Intel CK410 specification. It also provides support for PCI-Express and SATA. The part synthesizes several output frequencies from either a 14.31818 Mhz crystal or a 25 MHz crystal. The device can also be driven by a reference input clock instead of a crystal. It provides outputs with cycle-to-cycle jitter of less than 50 ps and output-to-output skew of less than 35 ps. The ICS9FG104 also provides a copy of the reference clock. Frequency selection can be accomplished via strap pins or SMBus control.
Block Diagram
XIN/CLKIN OSC X2 2
R EF OU T
PROGRAMMABLE SPREAD PLL
STOP LOGIC
4 DIF(3:0)
SPREAD SEL14M_25M# DIF_STOP# FS(2:0) SDATA SCLK CONTROL LOGIC
IREF
Power Groups
Pin Number VDD GND 3 4 9,21 10,20 28 27 Description REFOUT, Digital Inputs DIF Outputs IREF, Analog VDD, GND for PLL Core
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Integrated Circuit Systems, Inc.
ICS9FG104
Absolute Max
Symbol VDD_A VDD_In Ts Tambient Tcase ESD prot Parameter 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection human body model Min GND - 0.5 -65 0 Max VDD + 0.5V VDD + 0.5V 150 70 115 Units V V C C C V
2000
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current SYMBOL VIH VIL IIH IIL1 Input Low Current IIL2 CONDITIONS MIN 3.3 V +/-5% 2 VSS - 0.3 3.3 V +/-5% VIN = VDD -5 VIN = 0 V; Inputs with no pull-up -5 resistors VIN = 0 V; Inputs with pull-up -200 resistors Full Active, CL = Full load; f = 400 MHz Full Active, CL = Full load; f = 100 MHz All outputs stopped driven All outputs stopped Hi-Z VDD = 3.3 V 14 Logic Inputs Output pin capacitance From VDD Power-Up and after input clock stabilization to 1st clock Triangular Modulation DIF output enable after DIF_Stop# de-assertion 20% to 80% of VDD 1.5 TYP MAX
VDD + 0.3
0.8 5
UNITS NOTES V 1 V 1 uA 1 uA uA 1 1 1 1 1 1 3 1 1 1 1,2 1 1 1
125 110 106 48
150 125 120 60 25 7 5 6 1.8
mA mA mA mA MHz nH pF pF ms kHz ns ns
IDD3.3OP Operating Supply Current IDD3.3STOP Input Frequency3 Pin Inductance1 Input/Output Capacitance1 Clk Stabilization1,2 Modulation Frequency DIF output enable Input Rise and Fall times
1 2
Fi Lpin CIN COUT TSTAB fMOD tDIFOE tR/tF
30
33 15 5
Guaranteed by design, not 100% tested in production. See timing diagrams for timing requirements. 3 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz or 25 MHz to meet
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Integrated Circuit Systems, Inc.
ICS9FG104
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, REF = 475 PARAMETER Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy SYMBOL Zo
1
CONDITIONS VO = Vx Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. Crossing variation over all edges see Tperiod min-max values 400MHz nominal 400MHz spread 333.33MHz nominal 333.33MHz spread 266.66MHz nominal 266.66MHz spread 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 400MHz nominal/spread 333.33MHz nominal/spread 266.66MHz nominal/spread 200MHz nominal/spread 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V
MIN 3000 660 -150 -300 250
TYP
MAX 850
UNITS mV
NOTES 1 1 1
VHigh VLow Vovs Vuds Vcross(abs) d-Vcross ppm
150 1150 550 140 mV mV mV ppm ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps % ps ps ps ps
1 1 1 1 1,2 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1 1 1 1 1 4 4 4 1
Average period
Tperiod
Absolute min period
Tabsmin
Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle Skew, output to output Jitter, PCI-e SRC phase Jitter, PCI-e SRC phase Jitter, Cycle to cycle
1
tr tf d-tr d-tf dt3 tsk3 tjPCI-ephase14 tjPCI-ephase25 tjcyc-cyc
-300 2.4993 2.4993 2.9991 2.9991 3.7489 3.7489 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 2.4143 2.9141 3.6639 4.8735 5.8732 7.3728 9.8720 175 175
300 2.5008 2.5133 3.0009 3.016 3.7511 3.77 5.0015 5.0266 6.0018 6.0320 7.5023 5.4000 10.0030 10.0533
Measured Differentially VT = 50% 22MHz/1.5MHz/1.5MHz/10ns, 14.31818 MHz REF Clock 22MHz/1.5MHz/1.5MHz/10ns, 25 MHz REF Clock Measured Differentially
45
700 700 125 125 55 35 42 39 50
Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz or 25 MHz
3 4
Figures are for down spread. This figure is the peak-to-peak phase jitter as defined by PCI-SIG for a PCI Express reference clock. Please visit http://www.pcisig.com for additional details
0839D--06/02/05
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Integrated Circuit Systems, Inc.
ICS9FG104
Electrical Characteristics - REF-14.318/25 MHz
T A = 0 - 70C; V DD = 3.3 V +/-5% ; C L = 30 pF (unless otherwise specified) SYMBO PARAMETER CONDITIONS MIN TYP MAX UNITS Notes L ppm see Tperiod min-max values -300 0 300 ppm 1 Long Accuracy 14.318MHz output nominal 69.8270 69.8413 69.8550 ns 1 Clock period T period 25.000MHz output nominal 39.9880 40.0000 40.0120 ns 1 Output High Voltage V OH I OH = -1 mA 2.4 V 1 I OL = 1 mA 0.4 V 1 Output Low Voltage V OL V OH @MIN = 1.0 V, Output High Current I OH -29 -23 mA 1 V OH@MAX = 3.135 V V OL @MIN = 1.95 V, 29 27 mA 1 Output Low Current I OL V OL @MAX = 0.4 V V OL = 0.4 V, V OH = 2.4 V 1 1.6 2 ns 1 Rise Time t r1 Fall Time t f1 V OH = 2.4 V, V OL = 0.4 V 1 1.6 2 ns 1,2 Duty Cycle Jitter
1 2
dt1 t jc yc -cy c
V T = 1.5 V V T = 1.5 V
45
52.5 150
55 200
% ps
1,2 1
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz or 25 MHz
0839D--06/02/05
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Integrated Circuit Systems, Inc.
ICS9FG104
General SMBus serial interface information for the ICS9FG104 How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address DC (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address DC (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address DD (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controlle r (Host) starT bit T Slave Address DC(H ) W Rite WR Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Sla ve /Re ce ive r)
Index Block Read Operation
Controlle r (Host) T starT bit Slave Address DC(H ) WR W Rite Beginning Byte = N ACK RT Repeat starT Slave Address DD(H ) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Sla ve /Re ce ive r)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P Not acknowledge stoP bit
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Integrated Circuit Systems, Inc.
ICS9FG104
SMBus Table: Device Control Register, READ/WRITE ADDRESS (DC/DD) 0 1 Byte 0 Pin # Name Control Function Type 1 SEL14M_25M# 17 RW Bit 7 See Frequency (FS3) 1 Selection Table, 6 RW Bit 6 FS2 Page 1 RW 24 Bit 5 FS11 1 RW 25 Bit 4 FS0 16 RW Off On Bit 3 Spread Enable1 Enable Software Control of Frequency, Spread Enable (Spread Type always Software Control) DIF_STOP# drive mode SPREAD TYPE Hardware Software Select Select Driven Down Hi-Z Center
PWD Pin 17 Pin 6 Pin 24 Pin 25 Pin 16
Bit 2
RW
0
Bit 1 Bit 0
RW RW
0 0
Notes: 1. These bits reflect the state of the corresponding pins at power up, but may be written to if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin. SMBus Table: Output Enable Register Pin # Name Control Function Byte 1 Reserved Bit 7 DIF_3 EN Output Enable Bit 6 DIF_2 EN Output Enable Bit 5 Reserved Bit 4 Reserved Bit 3 DIF_1 EN Output Enable Bit 2 DIF_0 EN Output Enable Bit 1 Reserved Bit 0 SMBus Table: Output Stop Control Register Pin # Name Control Function Byte 2 Reserved Bit 7 DIF_3 STOP EN Free Run/ Stop Enable Bit 6 DIF_2 STOP EN Free Run/ Stop Enable Bit 5 Reserved Bit 4 Reserved Bit 3 DIF_1 STOP EN Free Run/ Stop Enable Bit 2 DIF_0 STOP EN Free Run/ Stop Enable Bit 1 Reserved Bit 0
Type RW RW
0 Disable Disable
1 Enable Enable
RW RW
Disable Disable
Enable Enable
PWD 1 1 1 1 1 1 1 1
Type RW RW
0
1
Free-run Stop-able Free-run Stop-able
RW RW
Free-run Stop-able Free-run Stop-able
PWD 0 0 0 0 0 0 0 0
0839D--06/02/05
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Integrated Circuit Systems, Inc.
ICS9FG104
SMBus Table: Frequency Select Readback Register Pin # Name Control Function Byte 3 1 SEL14M_25M# 17 State of pin 17 Bit 7 (FS3) 6 State of pin 6 Bit 6 FS21 24 State of pin 24 Bit 5 FS11 25 State of pin 25 Bit 4 FS01 16 State of pin 16 Bit 3 SPREAD1 Reserved Bit 2 Reserved Bit 1 Reserved Bit 0
Type R R R R R
0
1
PWD Pin 17 Pin 6 Pin 24 Pin 25 Pin 16 0 0 0
See Frequency Selection Table, Page 1 Off On
Notes: 1. These bits reflect the state of the corresponding pins, regardless of whether software programming is enabled or not. SMBus Table: Vendor & Revision ID Register Pin # Name Control Function Byte 4 RID3 Bit 7 RID2 Bit 6 REVISION ID RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VENDOR ID VID1 Bit 1 VID0 Bit 0 SMBus Table: DEVICE ID Byte 5 Pin # Name DID7 Bit 7 DID6 Bit 6 DID5 Bit 5 DID4 Bit 4 DID3 Bit 3 DID2 Bit 2 DID1 Bit 1 DID0 Bit 0
Type R R R R R R R R
0 -
1 -
PWD X X X X 0 0 0 1
Control Function
Device ID = 08 hex
Type RW RW RW RW RW RW RW RW
0 -
1 -
PWD 0 0 0 0 1 0 0 0
0839D--06/02/05
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Integrated Circuit Systems, Inc.
ICS9FG104
SMBus Table: Byte Count Register Byte 6 Pin # Name BC7 Bit 7 BC6 Bit 6 BC5 Bit 5 BC4 Bit 4 BC3 Bit 3 BC2 Bit 2 BC1 Bit 1 BC0 Bit 0 SMBus Table: Reserved Register Byte 7 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBus Table: Reserved Register Pin # Name Byte 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type RW RW Writing to this register RW will configure how RW many bytes will be RW read back, default is RW 07 = 7 bytes. RW RW
Control Function
0 -
1 -
PWD 0 0 0 0 0 1 1 1
Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Type
0
1
PWD 0 0 0 0 0 0 0 0
Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Type
0
1
PWD 0 0 0 0 0 0 0 0
SMBus Table: M/N Programming Enable Byte 9 Pin # Name Control Function M/N_Enable M/N Prog. Enable Bit 7 Reserved Bit 6 REFOUT_En REFOUT Enable 5 Bit 5 Reserved Bit 4 Reserved Bit 3 Reserved Bit 2 Reserved Bit 1 Reserved Bit 0
Type 0 RW Disable RW Disable
1 Enable Enable
PWD 0 1 1 0 0 0 0 0
0839D--06/02/05
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Integrated Circuit Systems, Inc.
ICS9FG104
SMBus Table: PLL Frequency Control Pin # Name Byte 10 PLL N Div8 Bit 7 PLL N Div9 Bit 6 PLL M Div5 Bit 5 PLL M Div4 Bit 4 PLL M Div3 Bit 3 PLL M Div2 Bit 2 PLL M Div1 Bit 1 Bit 0 PLL M Div0
Register Control Function N Divider Prog bit 8 N Divider Prog bit 9
M Divider Programming bit (5:0)
Type RW RW RW RW RW RW RW
0
1
The decimal representation of M and N Divider in Byte 11 and 12 will configure the PLL VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / RW [MDiv(5:0)+2]
PWD X X X X X X X X
SMBus Table: PLL Frequency Control Register Pin # Name Control Function Type 0 1 PWD Byte 11 The decimal PLL N Div7 RW X Bit 7 PLL N Div6 RW representation of M and X Bit 6 N Divider in Byte 11 and PLL N Div5 RW 12 will configure the PLL X Bit 5 N Divider PLL N Div4 RW X Bit 4 VCO frequency. Programming Byte11 RW Default at power up = PLL N Div3 X Bit 3 bit(7:0) and Byte10 PLL N Div2 RW latch-in or Byte 0 Rom X Bit 2 bit(7:6) PLL N Div1 RW table. VCO Frequency X Bit 1 Bit 0 PLL N Div0 RW
= 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2]
X
SMBus Table: PLL Spread Spectrum Control Register Pin # Name Control Function Type 0 1 PWD Byte 12 PLL SSP7 RW X Bit 7 PLL SSP6 RW X Bit 6 These Spread PLL SSP5 RW X Bit 5 Spectrum bits in Byte Spread Spectrum PLL SSP4 RW 13 and 14 will program X Bit 4 Programming bit(7:0) RW the spread pecentage PLL SSP3 X Bit 3 of PLL PLL SSP2 RW X Bit 2 PLL SSP1 RW X Bit 1 PLL SSP0 RW X Bit 0 SMBus Table: PLL Spread Spectrum Control Register Pin # Name Control Function Byte 13 Reserved Bit 7 PLL SSP14 Bit 6 PLL SSP13 Bit 5 PLL SSP12 Bit 4 Spread Spectrum PLL SSP11 Bit 3 Programming bit(14:8) PLL SSP10 Bit 2 PLL SSP9 Bit 1 PLL SSP8 Bit 0
Type RW RW RW RW RW RW RW
PWD 0 X X These Spread X Spectrum bits in Byte 13 and 14 will program X the spread pecentage X of PLL X X
0
1
0839D--06/02/05
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Integrated Circuit Systems, Inc.
ICS9FG104
DIF_STOP# - Assertion (transition from '1' to '0')
Asserting DIF_STOP# pin stops all DIF outputs that are set to be stoppable after their next transition. When the SMBus DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '0', DIF output will stop DIF_True = HIGH and DIF_Complement = LOW. When the SMBus DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '1', DIFoutputs will be tri-stated.
DIF_STOP# DIF DIF#
DIF_STOP# - De-assertion (transition from '0' to '1')
With the de-assertion of DIF_STOP# all stopped DIF outputs will resume without a glitch. The maximum latency from the de-assertion to active outputs is 2 - 6 DIF clock periods. If the control register tristate bit corresponding to the output of interest is programmed to '1', then the stopped DIF outputs will be driven High within 15nS of DIF_Stop# de-assertion to a voltage greater than 200mV.
DIF_Stop# DIF DIF#
DIF Internal
Tdrive_DIF_Stop, 15nS >200mV
0839D--06/02/05
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Integrated Circuit Systems, Inc.
ICS9FG104
N
c
L
SYMBOL A A1 A2 b c D E E1 e L N VARIATIONS
E1 INDEX AREA
E
12 h x 45 D
A A1
5.3 mm. Body, 0.65 mm. Pitch SSOP (204mil) (25.6 mil) In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX -2.00 -.079 0.05 -.002 -1.65 1.85 .065 .073 0.22 0.38 .009 .015 0.09 0.25 .0035 .010 SEE VARIATIONS SEE VARIATIONS 7.40 8.20 .291 .323 5.00 5.60 .197 .220 0.0256 BASIC 0.65 BASIC 0.55 0.95 .022 .037 SEE VARIATIONS SEE VARIATIONS 0 8 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 28
D mm. MIN 9.90 MAX 10.50 MIN .390
D (inch) MAX .413
Reference Doc.: JEDEC Publication 95, MO-150
Ordering Information
ICS9FG104yFLFT
Example:
ICS XXXX y F - LF T
Designation for tape and reel packaging RoHS Compliant (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers) Prefix ICS, AV = Standard Device
0839D--06/02/05
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Integrated Circuit Systems, Inc.
ICS9FG104
N
c
L
SYMBOL A A1 A2 b c D E E1 e L N aaa VARIATIONS N
INDEX AREA
E1
E
12 D
4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil) (25.6 mil) In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX -1.20 -.047 0.05 0.15 .002 .006 0.80 1.05 .032 .041 0.19 0.30 .007 .012 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS 6.40 BASIC 0.252 BASIC 4.30 4.50 .169 .177 0.65 BASIC 0.0256 BASIC 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS 0 8 0 8 -0.10 -.004
A2 A1
A
D mm. MIN 9.60 MAX 9.80 MIN .378
D (inch) MAX .386
-Ce
b SEATING PLANE
28
Reference Doc.: JEDEC Publication 95, MO-153
10-0035
aaa C
Ordering Information
ICS9FG104yGLFT
Example:
ICS XXXX y G LF T
Designation for tape and reel packaging RoHS Compliant (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers) Prefix ICS, AV = Standard Device
0839D--06/02/05
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Integrated Circuit Systems, Inc.
ICS9FG104
Revision History
Rev. D Issue Date Description 1. Updated SMBus Byte 3 bit 7, 5, 4 and 3. 6/2/2005 2. Updated LF Ordering Information to RoHS Compliant. Page # 9, 13-14
0839D--06/02/05
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